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ISL4260E
Data Sheet August 2004 FN6035.1
QFN Packaged, 15kV ESD Protected, +3V to +5.5V, 150nA, 250kbps, RS-232 Transmitters/Receivers with Separate Logic Supply
The ISL4260E contains 3.0V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Targeted applications are PDAs, Palmtops, and cell phones where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with a manual powerdown function reduces the standby supply current to a 150nA trickle. Tiny 5mm x 5mm Quad Flat NoLead (QFN) packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. The ISL4260E features a VL pin that adjusts the logic pin (see Pin Descriptions table) output levels and input thresholds to values compatible with the VCC powering the external logic (e.g., a UART). The single pin powerdown function (SHDN = 0) disables all the receiver and transmitter outputs, while shutting down the charge pump to minimize supply current drain. Table 1 summarizes the features of the ISL4260E, while Application Note AN9863 summarizes the features of each device comprising the 3V RS-232 family.
Features
* Available in Near Chip Scale QFN (5mmx5mm) Package * VL Pin for Compatibility with Mixed Voltage Systems * ESD Protection for RS-232 I/O Pins to 15kV (IEC61000) * Single SHDN Pin Disables Transmitters and Receivers * Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V * On-Chip Charge Pumps Require Only Four External 0.1F Capacitors * Receiver Hysteresis For Improved Noise Immunity * Very Low Supply Current . . . . . . . . . . . . . . . . . . . . 300A * Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps * Wide Power Supply Range. . . . . . . . Single +3V to +5.5V * Low Supply Current in Powerdown State . . . . . . . . .150nA * Pb-free available
Applications
* Any System Requiring RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Digital Cameras - PDAs and PDA Cradles - Cellular/Mobile Phones
Ordering Information
PART NUMBER ISL4260EIR ISL4260EIRZ (See Note) TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 32 Lead QFN 32 Lead QFN (Pb-free) PKG. NO. L32.5x5 L32.5x5
*Add "-T" suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
TABLE 1. SUMMARY OF FEATURES PART NUMBER ISL4260E NO. OF NO. OF DATA RATE Rx. ENABLE Tx. Rx. (kbps) FUNCTION? 3 2 250 NO VL LOGIC SUPPLY PIN? YES MANUAL AUTOMATIC POWER- DOWN? POWERDOWN FUNCTION? YES NO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2004. All Rights Reserved
ISL4260E Pinout
ISL4260E (QFN) TOP VIEW
SHDN C1+ C1GND 26 VCC NC V+ NC 25 24 23 22 21 20 19 18 17 9 NC 10 T3IN 11 NC 12 R2OUT 13 R1OUT 14 NC 15 VL 16 NC NC T1OUT T2OUT T3OUT NC R1IN R2IN NC
32 NC C2+ C2VT1IN T2IN NC NC 1 2 3 4 5 6 7 8
31
30
29
28
27
Pin Descriptions
PIN VCC V+ VGND C1+ C1C2+ C2TIN TOUT RIN ROUT VL SHDN NC System power supply input (3.0V to 5.5V). Internally generated positive transmitter supply (+5.5V). Internally generated negative transmitter supply (-5.5V). Ground connection. External capacitor (voltage doubler) is connected to this lead. External capacitor (voltage doubler) is connected to this lead. External capacitor (voltage inverter) is connected to this lead. External capacitor (voltage inverter) is connected to this lead. TTL/CMOS compatible transmitter Inputs. The switching point is a function of the VL voltage. 15kV ESD Protected, RS-232 level (nominally 5.5V) transmitter outputs. 15kV ESD Protected, RS-232 compatible receiver inputs. TTL/CMOS level receiver outputs. Swings between GND and VL. Logic-Level Supply. All TTL/CMOS inputs and outputs are powered by this supply. Active low TTL/CMOS input to tri-state receiver and transmitter outputs and to shut down the on-board power supply to place device in low power mode. The switching point is a function of the VL voltage. No Connection FUNCTION
2
ISL4260E Typical Operating Circuit
+3.3V to +5V
+ 0.1F 29 + 31 2 + 3 5 C1+ C1C2+ C2-
27 VCC 30 V+ 4 + 23 + C3 0.1F C4 0.1F
C1 0.1F C2 0.1F
VT1
T1IN
T1OUT
T2IN TTL/CMOS LOGIC LEVELS
6
T2
22 T2OUT
T3IN
10
T3
21 T3OUT
RS-232 LEVELS
R1 R1OUT 13 5k 12 R2OUT 5k VL SHDN GND 26 R2
19
R1IN
18 R2IN
LOGIC VCC 0.1F
15 +
28
VCC
3
ISL4260E
Absolute Maximum Ratings
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Input Voltages TIN, SHDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VL +0.3V) Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
32 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 32 Moisture Sensitivity (see Technical Brief TB363) QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range ISL4260EIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379, and Tech Brief TB389.
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1F, VL = VCC; Unless Otherwise Specified. Typicals are at TA = 25oC, VCC = VL = 3.3V TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS Supply Current, Powerdown Supply Current
SHDN = GND, All Inputs at VCC or GND All Outputs Unloaded, SHDN = VCC, VCC = 3.15V
25 25
-
0.15 0.3
1 1
A mA
LOGIC AND TRANSMITTER INPUTS Input Logic Threshold Low TIN, SHDN VL = 3.3V or 5V VL = 2.5V Input Logic Threshold High TIN, SHDN VL = 5V VL = 3.3V VL = 2.5V VL = 1.8V Transmitter Input Hysteresis Input Leakage Current RECEIVER OUTPUTS Output Leakage Current Output Voltage Low Output Voltage High RECEIVER INPUTS Input Voltage Range Input Threshold Low VL = 5.0V VL = 3.3V Input Threshold High VL = 5.0V VL = 3.3V Input Hysteresis Input Resistance Full 25 25 25 25 25 25 -25 0.8 0.6 3 1.5 1.2 1.8 1.5 0.5 5 25 2.4 2.4 7 V V V V V V k VCC = 0V or 3V to 5.5V, SHDN = GND IOUT = 1.6mA IOUT = -1.0mA Full Full Full VL - 0.6 0.05 VL - 0.1 10 0.4 A V V TIN, SHDN Full Full Full Full Full 25 25 Full 2.4 2.0 1.4 0.9 0.5 0.01 0.8 0.6 1 V V V V V V V A
4
ISL4260E
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1F, VL = VCC; Unless Otherwise Specified. Typicals are at TA = 25oC, VCC = VL = 3.3V (Continued) TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS
PARAMETER TRANSMITTER OUTPUTS Output Voltage Swing Output Resistance Output Short-Circuit Current Output Leakage Current TIMING CHARACTERISTICS Maximum Data Rate Receiver Propagation Delay
All Transmitter Outputs Loaded with 3k to Ground VCC = V+ = V- = 0V, Transmitter Output = 2V Shorted to GND VOUT = 12V, VCC = 0V or 3V to 5.5V, SHDN = GND
Full Full Full Full
5.0 300 -
5.4 10M -
60 25
V mA A
RL = 3k, CL = 1000pF, One Transmitter Switching Receiver Input to Receiver Output, CL = 150pF tPHL tPLH
Full 25 25 25 25
250 6 4
500 0.15 0.15 200 200 100 100 50 18 13
30 30
kbps s s ns ns s ns ns V/s V/s
Receiver Output Enable Time Receiver Output Disable Time Transmitter Output Enable Time Transmitter Skew Receiver Skew Transition Region Slew Rate From SHDN Rising Edge to TOUT = 3.7V tPHL - tPLH (Note 2) tPHL - tPLH CL = 150pF to 1000pF RL = 3k to 7k, Measured From 3V to -3V or CL = 150pF to 2500pF -3V to 3V, VCC = 3.3V
25 25 25 25 25
ESD PERFORMANCE RS-232 Pins (TOUT, RIN) Human Body Model IEC61000-4-2 Air Gap Discharge IEC61000-4-2 Contact Discharge NOTE: 2. Transmitter skew is measured at the transmitter zero crossing points. 25 25 25 15 15 8 kV kV kV
Detailed Description
The ISL4260E operates from a single +3V to +5.5V supply, guarantees a 250kbps minimum data rate, requires only four small external 0.1F capacitors, features low power consumption, and meets all ElA RS-232C and V.28 specifications. The circuit is divided into three sections: The charge pump, the transmitters, and the receivers.
up to the nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232 output levels. Coupled with the on-chip 5.5V supplies, these transmitters deliver true RS-232 levels over a wide range of single supply system voltages. All transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (see Table 2). These outputs may be driven to 12V when disabled. All devices guarantee a 250kbps data rate for full load conditions (3k and 1000pF), VCC 3.0V, with one transmitter operating at full speed. Under more typical conditions of VCC 3.3V, RL = 3k, and CL = 250pF, one transmitter easily operates at 1.25Mbps. The transmitter input threshold is set by the voltage applied to the VL pin. Transmitter inputs float if left unconnected
Charge-Pump
Intersil's new ISL4260E utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate 5.5V transmitter supplies from a VCC supply as low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the 10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1F capacitors for the voltage doubler and inverter functions over the full VCC range; other capacitor combinations can be used as shown in Table 3. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped
5
ISL4260E
(there are no pull-up resistors), and may cause ICC increases. Connect unused inputs to GND for the best performance.
TABLE 2. POWERDOWN TRUTH TABLE SHDN TRANSMITTER RECEIVER INPUT OUTPUTS OUTPUTS MODE OF OPERATION L H High-Z Active High-Z Active Manual Powerdown Normal Operation
VCC SHDN PWR MGT LOGIC I/O CHIP POWER SUPPLY VL ISL4260E
Receivers
The ISL4260E contains standard inverting receivers that convert RS-232 signals to CMOS output levels and accept inputs up to 25V while presenting the required 3k to 7k input impedance (see Figure 1) even if the power is off (VCC = 0V). The receivers' Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. Receiver outputs swing from GND to VL, and tristate in powerdown.
VL RXIN -25V VRIN +25V GND 5k RXOUT GND VROUT VL
CPU
I/O UART
FIGURE 2. CONNECTIONS FOR MANUAL POWERDOWN
VL Logic Supply Input
Unlike other RS-232 interface devices where the CMOS outputs swing between 0 and VCC, the ISL4260E features a separate logic supply input (VL; 1.8V to 5V, regardless of VCC) that sets VOH for the receiver outputs. Connecting VL to a host logic supply lower than VCC, prevents the ISL4260E outputs from forward biasing the input diodes of a logic device powered by that lower supply. Connecting VL to a logic supply greater than VCC ensures that the receiver output levels are compatible even with the CMOS input VIH of AC, HC, and CD4000 devices. Note that the VL supply current increases to 100A with VL = 5V and VCC = 3.3V (see Figure 11). VL also powers the transmitter and logic inputs, thereby setting their switching thresholds to levels compatible with the logic supply. This separate logic supply pin allows a great deal of flexibility in interfacing to systems with different logic supplies. If logic translation isn't required, connect VL to the ISL4260E VCC.
FIGURE 1. RECEIVER CONNECTIONS
Low Power Operation
This 3V device requires a nominal supply current of 0.3mA, even at VCC = 5.5V, during normal operation (not in powerdown mode). This is considerably less than the 11mA current required by comparable 5V RS-232 devices, allowing users to reduce system power simply by replacing the old style device with the ISL4260E in new designs.
Powerdown Functionality
The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 150nA, because the on-chip charge pump turns off (V+ collapses to VCC, V- collapses to GND), and the transmitter and receiver outputs tristate. This micropower mode makes these devices ideal for battery powered and portable applications.
Capacitor Selection
The ISL4260E charge pumps only require 0.1F capacitors for the full operational voltage range. Table 3 lists other acceptable capacitor values for various supply voltage ranges. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption.
TABLE 3. REQUIRED CAPACITOR VALUES VCC (V) 3.0 to 3.6 4.5 to 5.5 3.0 to 5.5 C1 (F) 0.1 0.047 0.22 C2, C3, C4 (F) 0.1 0.33 1
Software Controlled (Manual) Powerdown
The ISL4260E may be forced into its low power, standby state via a simple shutdown (SHDN) pin (see Figure 2). Driving this pin high enables normal operation, while driving it low forces the IC into its powerdown state. The time required to exit powerdown, and resume transmission is less than 100s. Connect SHDN to VCC if the powerdown function isn't needed.
6
ISL4260E
When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor's equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-.
VCC 0.1F
+
+ C1
C1+ C1-
VCC
VL
V+
+ C3
Power Supply Decoupling
In most circumstances a 0.1F bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1. Connect the bypass capacitor as close as possible to the IC.
C2
ISL4260E + C2+ C2TIN ROUT TOUT RIN 5k VCC SHDN 1000pF VC4 +
Transmitter Outputs when Exiting Powerdown
Figure 3 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3k in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V.
FIGURE 4. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV. T1IN
5V/DIV
SHDN T1 T1OUT
2V/DIV
R1OUT VCC = +3.3V C1 - C4 = 0.1F 5s/DIV. T2
FIGURE 5. LOOPBACK TEST AT 120kbps
VCC = +3.3V C1 - C4 = 0.1F TIME (20s/DIV.) 5V/DIV. T1IN
FIGURE 3. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN
High Data Rates
The ISL4260E maintains the RS-232 5V minimum transmitter output voltages even at high data rates. Figure 4 details a transmitter loopback test circuit, and Figure 5 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 6 shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 receiver.
T1OUT
R1OUT VCC = +3.3V C1 - C4 = 0.1F 2s/DIV.
FIGURE 6. LOOPBACK TEST AT 250kbps
7
ISL4260E Interconnection with 3V and 5V Logic
Standard 3.3V powered RS-232 devices interface well with 3V and 5V powered TTL compatible logic families (e.g., ACT and HCT), but the logic outputs (e.g., ROUTS) fail to reach the VIH level of 5V powered CMOS families like HC, AC, and CD4000. The ISL4260E VL supply pin solves this problem. By connecting VL to the same supply (1.8V to 5V) powering the logic device, the ISL4260E logic outputs will swing from GND to the logic VCC. respect to all other pins. The RS-232 pins on "E" family devices can withstand HBM ESD events to 15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-232 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device's RS-232 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-232 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The "E" device RS-232 pins withstand 15kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than 8kV. All "E" family devices survive 8kV contact discharges on the RS-232 pins.
15kV ESD Protection
All pins on the 3V interface devices include ESD protection structures, but the ISL4260E incorporates advanced structures which allow the RS-232 pins (transmitter outputs and receiver inputs) to survive ESD events up to 15kV. The RS-232 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and don't interfere with RS-232 signals as large as 25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a 1.5k current limiting resistor, making the test less severe than the IEC61000 test which utilizes a 330 limiting resistor. The HBM method determines an ICs ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with
Typical Performance Curves
6.0 TRANSMITTER OUTPUT VOLTAGE (V) 4.0 2.0 1 TRANSMITTER AT 250kbps OTHER TRANSMITTERS AT 30kbps 0 -2.0 -4.0 -6.0
VCC = 3.3V, TA = 25oC
30 VOUT+ 25 SLEW RATE (V/s)
20 +SLEW -SLEW 10
15
VOUT -
0
1000
2000
3000
4000
5000
5 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 7. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE
FIGURE 8. SLEW RATE vs LOAD CAPACITANCE
8
ISL4260E Typical Performance Curves
45 40 250kbps SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 35 30 120kbps 25 20 20kbps 15 10 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF)
VCC = 3.3V, TA = 25oC (Continued)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.5
NO LOAD ALL OUTPUTS STATIC
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
FIGURE 9. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA
10m 1m 100 10 IL (A) VL VCC 1 VL > VCC NO LOAD ALL OUTPUTS STATIC VCC = 3.3V
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
100n 10n 1n 2.0
2.5
3.0
3.5
4.0
4.5 VL (V)
5.0
5.5
6.0
6.5
7.0
FIGURE 11. VL SUPPLY CURRENT vs VL VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP) GND TRANSISTOR COUNT 422 PROCESS Si Gate CMOS
9
ISL4260E Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 8 0.25 0.30 2.95 2.95 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.50 BSC 0.40 32 8 8 0.60 12 0.50 0.15 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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